In TTL (Transistor-Transistor-Logic) level or CMOS (Complementary Metal-Oxide-Semiconductor) level arrangements widely used for interfaces between CMOS semiconductor integrated circuit devices, irregular reflections are caused at both ends of a signal transmission line, so that it is known that data transfer frequencies are limited in performance to 60 MHz to 100 MHz at most. On the other hand, in pseudo ECL (Emitter Coupled Logic) and GTL (Gurnning Transceiver Logic) arrangements, the data transfer frequency is raised by connecting a terminating resistor to the end of a signal transmission line to prevent the reflection of the waveform.
However, in order to reduce power consumption, the signal amplitude is limited to about 0.8 V (volt) relative to 5 V (volt) or 3.3 V (volt) of the operating or the supply voltage of a semiconductor integrated circuit device.
A pseudo ECL arrangement is described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, FEBRUARY. 1988, PP. 59-67. A GTL arrangement is disclosed in U.S. Pat. No. 5,023,488 (Jan. 11, 1991).